This invention relates to input/output interfaces for integrated circuits. More particularly, this invention relates to a system and method for distributing clock signals in a programmable logic device (PLD) that employs a multiple data rate interface.
Various high speed interface mechanisms have been developed to increase the speed of data transfer and data throughput between integrated devices. One such mechanism is a multiple data rate interface scheme. In a multiple data rate interface scheme, two or more bits of data are transferred during each clock period.
One example of multiple data rate technology is the double data rate (“DDR”) technology. In DDR, two data operations are performed in one clock cycle, thus achieving twice the data throughput. This technology has enhanced the bandwidth performance of integrated circuits used in a wide array of applications from computers to communication systems. The DDR technique is being employed in, for example, today's synchronous dynamic random access memory (SDRAM) circuits.
FIG. 1 illustrates the timing relationship between the data and clock signals in a DDR interface. DDR implementation processes I/O data (also referred to as DQ signals) using both the rising edge and the falling edge of a clock signal (the DQS signal) that functions as a data strobe to control the timing of data transfer. DQS is normally edge-aligned with DQ for a DDR interface operating in the read mode and center aligned for a DDR interface operating in the write mode.
For optimum sampling of data, internal to the integrated circuit, DQS is delayed by one-quarter of the clock period to achieve a 90 degree phase shift between the edges of DQ and DQS. This ensures that the DQS edge occurs as close to the center of the DQ pulse as possible as shown in FIG. 1. It is desirable to implement this 90 degree phase shift as accurately and in as stable a manner as possible.
Generally, a programmable logic device having a multiple data rate interface includes a programmable logic core comprising an array of logic elements and a periphery that among other circuitry includes I/O circuitry. The I/O circuitry of a programmable logic device having a multiple data rate interface includes dedicated I/O registers for performing the functions associated with the multiple data rate interface. The DQS signal is applied to a phase locked loop (PLL) or a delay chain to generate the required phase shift and alignment. The DQ signals are applied directly to respective I/O registers whose clock inputs receive the phase-corrected DQS signal.
Where an application does not need a multiple data rate interface or where the application does not utilize all of the registers within the logic elements of the programmable logic core, the dedicated I/O registers take up valuable periphery space that may be used for other functions or that may be eliminated to reduce chip size. Thus, there is a need in the art for a multiple data rate interface that does not use dedicated I/O registers in the periphery of the device.